Permutation Networks as Application Specific Interconnection Networks for SIMD DSPs

Parallelization is one possibility to enhance the performance in processors. For singleinstruction-multiple-data (SIMD) processors one requirement is the possibility to parallelize algorithms so that one algorithm is partitioned to the parallel processing units of the processor. This means that data has to be exchanged between the processing units. Hence, these separate units have to be connected either logically with e.g. shared memory or physically with interconnection networks. Thus the possibility of parallel implementation of algorithms on a SIMD processor strongly depends on the possibility of data exchange. Intra processor connection for processors which comprise multiple processing units, needs lean implementation of networks, i.e. sparse networks with simple controllability. As an example, we look at the digital signal processor M3-DSP, which was a first prototype of the Concept for Application Tailored Signal Processors developed at Dresden University of Technology [8]. The M3-DSP comprises 16 single-instruction-multiple-data (SIMD) parallel processing units which use a vector memory. Data is exchanged via a physical interconnection network. Figure 1 shows a simplified block diagram of this parallel DSP. The vector memory can be accessed as a vector only, no element access is possible. The separate parallel data paths each have access to a corresponding vector register-file. Again, only vector access is possible. To exchange data between the parallel processing units, a connecting network is used to exchange data among the parallel units between memory and register file as well as between different registers of the register file. In SIMD processors single instructions are used to exchange data over some or all parallel processing units. We call such instructions data transfer instructions. An example for such an instruction is a rotation to the left data transfer which transfers the data of a processing